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19-1777; Rev 0; 1/02
Quad, 10-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC
General Description
The MAX5841 is a quad, 10-bit voltage output, digitalto-analog converter (DAC) with an I2CTM-compatible, 2-wire interface that operates at clock rates up to 400kHz. The device operates from a single 2.7V to 5.5V supply and draws only 230A at VDD = 3.6V. A powerdown mode decreases current consumption to less than 1A. The MAX5841 features three software-selectable power-down output impedances: 100k, 1k, and high impedance. Other features include internal precision Rail-to-Rail(R) output buffers and a power-on reset (POR) circuit that powers up the DAC in the 100k power-down mode. The MAX5841 features a double-buffered I2C-compatible serial interface that allows multiple devices to share a single bus. All logic inputs are CMOS-logic compatible and buffered with Schmitt triggers, allowing direct interfacing to optocoupled and transformer-isolated interfaces. The MAX5841 minimizes digital noise feedthrough by disconnecting the clock (SCL) signal from the rest of the device when an address mismatch is detected. The MAX5841 is specified over the extended temperature range of -40C to +85C and is available in a miniature 10-pin MAX package. Refer to the MAX5842 data sheet for the 12-bit version. o Ultra-Low Supply Current 230A at VDD = 3.6V 280A at VDD = 5.5V o 300nA Low-Power Power-Down Mode o Single 2.7V to 5.5V Supply Voltage o Fast 400kHz I2C-Compatible 2-Wire Serial Interface o Schmitt-Trigger Inputs for Direct Interfacing to Optocouplers o Rail-to-Rail Output Buffer Amplifiers o Three Software-Selectable Power-Down Output Impedances 100k, 1k, and High Impedance o Read-Back Mode for Bus and Data Checking o Power-On Reset to Zero o 10-Pin MAX Package
Features
MAX5841
Ordering Information
PART MAX5841LEUB TEMP RANGE -40oC to +85oC PINPACKAGE 10 MAX 10 MAX ADDRESS 0111 10X 1011 10X
Applications
Digital Gain and Offset Adjustments Programmable Voltage and Current Sources Programmable Attenuation VCO/Varactor Diode Control Low-Cost Instrumentation Battery-Powered Equipment ATE
MAX5841MEUB -40oC to +85oC
Typical Operating Circuit
VDD C SDA VDD SCL RP RP
Pin Configuration
TOP VIEW
ADD 1 SCL VDD GND SDA 2 3 4 5 10 OUTD 9 OUTC OUTB OUTA REF
RS SCL RS SDA MAX5841 REF
VDD OUTA OUTB OUTC OUTD
MAX5841
8 7 6
RS SCL RS SDA REF
MAX5841
VDD OUTA OUTB OUTC OUTD
MAX
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd. I2C is a trademark of Philips Corp.
REF
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Quad, 10-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC MAX5841
ABSOLUTE MAXIMUM RATINGS
VDD, SCL, SDA to GND ............................................-0.3V to +6V OUT_, REF, ADD to GND..............................-0.3V to VDD + 0.3V Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70C) 10-Pin MAX (derate 5.6mW above +70C) ................444mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Maximum Junction Temperature .....................................+150C Lead Temperature (soldering 10s) ..................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +2.7V to +5.5V, GND = 0, VREF = VDD, RL = 5k, CL = 200pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +5V, TA = +25C.) (Note 1)
PARAMETER STATIC ACCURACY (NOTE 2) Resolution Integral Nonlinearity Differential Nonlinearity Zero-Code Error Zero-Code Error Tempco Gain Error Gain-Error Tempco Power-Supply Rejection Ratio DC Crosstalk REFERENCE INPUT Reference Input Voltage Range Reference Input Impedance Reference Current DAC OUTPUT Output Voltage Range DC Output Impedance Short-Circuit Current Wake-Up Time DAC Output Leakage Current DIGITAL INPUTS (SCL, SDA) Input High Voltage Input Low Voltage VIH VIL 0.7 VDD 0.3 VDD V V No load (Note 4) Code = 200 hex VDD = 5V, VOUT = full scale (short to GND) VDD = 3V, VOUT = full scale (short to GND) VDD = 5V VDD = 3V Power-down mode = high impedance, VDD = 5.5V, VOUT_ = VDD or GND 0 1.2 42.2 15.1 8 8 0.1 1 VDD V mA s A Power-down mode VREF 0 32 45 0.3 1 VDD V k A PSRR Code = 3FF hex, VDD = 4.5V to 5.5V GE Code = 3FF hex N INL DNL ZCE (Note 3) Guaranteed monotonic (Note 3) Code = 000 hex, VDD = 2.7V 6 2.3 -0.8 0.26 58.8 30 -3 10 0.5 4 0.5 40 Bits LSB LSB mV ppm/oC %FSR ppm/oC dB V SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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Quad, 10-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +5.5V, GND = 0, VREF = VDD, RL = 5k, CL = 200pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +5V, TA = 25C.)
PARAMETER Input Hysteresis Input Leakage Current Input Capacitance DIGITAL OUTPUT (SDA) Output Logic Low Voltage Three-State Leakage Current Three-State Output Capacitance DYNAMIC PERFORMANCE Voltage Output Slew Rate Voltage Output Settling Time Digital Feedthrough Digital-to-Analog Glitch Impulse DAC-to-DAC Crosstalk POWER SUPPLIES Supply Voltage Range Supply Current with No Load Power-Down Supply Current Serial Clock Frequency Bus Free Time Between STOP and START Conditions START Condition Hold Time SCL Pulse Width Low SCL Pulse Width High Repeated START Setup Time Data Hold Time Data Setup Time SDA and SCL Receiving Rise Time SDA and SCL Receiving Fall Time SDA Transmitting Fall Time STOP Condition Setup Time VDD IDD IDDPD fSCL tBUF tHD,STA tLOW tHIGH tSU,STA tHD,DAT tSU,DAT tr tf tf tSU,STO (Note 5) (Note 5) (Note 5) All digital inputs at 0 or VDD = 3.6V All digital inputs at 0 or VDD = 5.5V All digital inputs at 0 or VDD = 5.5V 0 1.3 0.6 1.3 0.6 0.6 0 100 0 0 20 + 0.1Cb 0.6 300 300 250 0.9 2.7 230 280 0.3 5.5 395 420 1 400 V A A kHz s s s s s s ns ns ns ns s SR To 1/2LSB code 100 hex to 300 hex or 300 hex to 100 hex (Note 5) Code = 000 hex, digital inputs from 0 to VDD Major carry transition (code = 1FF hex to 200 hex and 200 hex to 1FF hex) 0.5 4 0.2 12 2.4 12 V/s s nV-s nV-s nV-s VOL IL ISINK = 3mA Digital inputs = 0 or VDD 0.1 6 0.4 1 V A pF Digital inputs = 0 or VDD SYMBOL CONDITIONS MIN 0.05 VDD
MAX5841
TYP
MAX
UNITS V
0.1 6
1
A pF
TIMING CHARACTERISTICS (FIGURE 1)
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Quad, 10-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC MAX5841
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +5.5V, GND = 0, VREF = VDD, RL = 5k, CL = 200pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +5V, TA = 25C.)
PARAMETER Bus Capacitance Maximum Duration of Suppressed Pulse Widths SYMBOL Cb tSP (Note 5) 0 CONDITIONS MIN TYP MAX 400 50 UNITS pF ns
Note 1: Note 2: Note 3: Note 4: Note 5:
All devices are 100% production tested a at TA = +25C and are guaranteed by design for TA = TMIN to TMAX. Static specifications are tested with the output unloaded. Linearity is guaranteed from codes 29 to 995. Offset and gain error limit the FSR. Guaranteed by design. Not production tested.
Typical Operating Characteristics
(VDD = +5V, RL = 5k, TA = +25C.)
INTEGRAL NONLINEARITY vs. INPUT CODE
0.75 0.50 INL (LSB) INL (LSB) INL (LSB) 0.25 0 -0.25 -0.50 -0.75 -1.00 0 256 512 INPUT CODE 768 1024 0 2.7 3.4 4.1 4.8 5.5 SUPPLY VOLTAGE (V) 0 -40 -15 10 35 60 85 TEMPERATURE (C) 0.75 0.75
MAX5841 toc01
INTEGRAL NONLINEARITY vs. SUPPLY VOLTAGE
MAX5841 toc02
INTEGRAL NONLINEARITY vs. TEMPERATURE
MAX5841 toc03
1.00
1.25
1.25
1.00
1.00
0.50
0.50
0.25
0.25
DIFFERENTIAL NONLINEARITY vs. INPUT CODE
0.75 0.50 DNL (LSB) DNL (LSB)
MAX5841 toc04
DIFFERENTIAL NONLINEARITY vs. SUPPLY VOLTAGE
MAX5841 toc05
DIFFERENTIAL NONLINEARITY vs. TEMPERATURE
MAX5841 toc06
1.00
0
0
-0.1
-0.1
0 -0.25 -0.50 -0.75 -1.00 0 256 512 INPUT CODE 768 1024
-0.3
DNL (LSB) 3.4 4.1 4.8
0.25
-0.2
-0.2
-0.3
-0.4
-0.4
-0.5 2.7 5.5 SUPPLY VOLTAGE (V)
-0.5 -40 -15 10 35 60 85 TEMPERATURE (C)
4
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Quad, 10-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC
Typical Operating Characteristics (continued)
(VDD = +5V, RL = 5k, TA = +25C.)
ZERO-CODE ERROR vs. SUPPLY VOLTAGE
MAX5841 toc07
MAX5841
ZERO-CODE ERROR vs. TEMPERATURE
MAX5841 toc08
GAIN ERROR vs. SUPPLY VOLTAGE
MAX5841 toc09
10
10
-2.0
8 ZERO-CODE ERROR (mV)
8 ZERO-CODE ERROR (mV)
-1.6 GAIN ERROR (%FSR)
6
6
-1.2
4
4
-0.8
2 NO LOAD 0 2.7 3.4 4.1 4.8 5.5 SUPPLY VOLTAGE (V)
2 NO LOAD 0 -40 -15 10 35 60 85 TEMPERATURE (C)
-0.4 NO LOAD 2.7 3.4 4.1 4.8 5.5
0 SUPPLY VOLTAGE (V)
GAIN ERROR vs. TEMPERATURE
MAX5841 toc10
DAC OUTPUT VOLTAGE vs. OUTPUT SOURCE CURRENT (NOTE 6)
MAX5841 toc11
DAC OUTPUT VOLTAGE vs. OUTPUT SINK CURRENT (NOTE 6)
MAX5841 toc12
-2.0
6 5 DAC OUTPUT VOLTAGE (V) 4 3 2 1
2.5
DAC OUTPUT VOLTAGE (V)
-1.6 GAIN ERROR (%FSR)
2.0
-1.2
1.5
-0.8
1.0
-0.4 NO LOAD -40 -15 10 35 60 85
0.5 CODE = 3FF hex CODE = 100 hex 0 0 2 4 6 8 10 0 2 4 6 8 10 OUTPUT SOURCE CURRENT (mA) OUTPUT SINK CURRENT (mA)
0 TEMPERATURE (C)
0
SUPPLY CURRENT vs. INPUT CODE
MAX5841 toc13
SUPPLY CURRENT vs. TEMPERATURE
MAX5841 toc14
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5841 toc15
320
320
320
SUPPLY CURRENT (A)
SUPPLY CURRENT (A)
280
280
SUPPLY CURRENT (A)
300
300
300
280
260
260 N0 LOAD CODE = 3FF hex
260 CODE = 3FF hex NO LOAD 10 35 60 85 240 2.7 3.4 4.1 4.8 5.5 SUPPLY VOLTAGE (V)
240 0 205 410 615 820 1024 INPUT CODE
240 -40 -15 TEMPERATURE (C)
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Quad, 10-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC MAX5841
Typical Operating Characteristics (continued)
(VDD = +5V, RL = 5k, TA = +25C.)
POWER-DOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE
POWER-DOWN SUPPLY CURRENT (nA) ZOUT = HIGH IMPEDANCE NO LOAD 400
MAX5841 toc16
POWER-UP GLITCH
MAX5841 toc17
500
VDD
5V
300 TA = +25C 200
TA = -40C 0
100
OUT_ TA = +85C
10mV/div
0 2.7 3.4 4.1 4.8 5.5 100s/div SUPPLY VOLTAGE (V)
EXITING SHUTDOWN
MAX5841 toc18
MAJOR CARRY TRANSITION (POSITIVE)
MAX5841 toc19
OUT_
500mV/div
OUT_
5mV/div
CLOAD = 200pF CODE = 200 hex 2s/div
CLOAD = 200pF RL = 5k CODE = 1FF hex TO 200 hex 2s/div
MAJOR CARRY TRANSITION (NEGATIVE)
MAX5841 toc20
SETTLING TIME (POSITIVE)
MAX5841 toc21
OUT_
5mV/div
OUT_
500mV/div
CLOAD = 200pF RL = 5k CODE = 200 hex TO 1FF hex 2s/div
CLOAD = 200pF CODE = 100 hex TO 300 hex 2s/div
6
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Quad, 10-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC
Typical Operating Characteristics (continued)
(VDD = +5V, RL = 5k, TA = +25C.)
SETTLING TIME (NEGATIVE)
MAX5841 toc22
MAX5841
DIGITAL FEEDTHROUGH
MAX5841 toc23
SCL
2mV/div
OUT_
500mV/div
OUT_ CLOAD = 200pF CODE = 300 hex TO 100 hex 2s/div 40s/div CLOAD = 200pF fSCL = 12kHz CODE = 000 hex
2mV/div
CROSSTALK
MAX5841 toc24
VOUTA
2V/div
VOUTB
1mV/div
4s/div
Note 6: The ability to drive loads less than 5k is not implied.
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Quad, 10-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC MAX5841
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 NAME ADD SCL VDD GND SDA REF OUTA OUTB OUTC OUTD Serial Clock Input Power Supply Ground Bidirectional Serial Data Interface Reference Input DAC A Output DAC B Output DAC C Output DAC D Output FUNCTION Address Select. A logic high sets the address LSB to 1; a logic low sets the address LSB to zero.
Detailed Description
The MAX5841 is a quad, 10-bit, voltage-output DAC with an I2C/SMBus-compatible 2-wire interface. The device consists of a serial interface, power-down circuitry, four input and DAC registers, four 10-bit resistor string DACs, four unity-gain output buffers, and output resistor networks. The serial interface decodes the address and control bits, routing the data to the proper input or DAC register. Data can be directly written to the DAC register, immediately updating the device output, or can be written to the input register without changing the DAC output. Both registers retain data as long as the device is powered.
are set to zero scale and the device is powered down, with the output buffers disabled and the outputs pulled to GND through the 100k termination resistor. Following power-up, a wake-up command must be initiated before any conversions are performed.
Power-Down Modes
The MAX5841 has three software-controlled low-power power-down modes. All three modes disable the output buffers and disconnect the DAC resistor strings from REF, reducing supply current draw to 1A and the reference current draw to less than 1A. In power-down mode 0, the device output is high impedance. In power-down mode 1, the device output is internally pulled to GND by a 1k termination resistor. In powerdown mode 2, the device output is internally pulled to GND by a 100k termination resistor. Table 1 shows the power-down mode command words. Upon wake-up, the DAC output is restored to its previous value. Data is retained in the input and DAC registers during power-down mode.
DAC Operation
The MAX5841 uses a segmented resistor string DAC architecture, which saves power in the overall system and guarantees output monotonicity. The MAX5841's input coding is straight binary, with the output voltage given by the following equation: V x (D) VOUT _ = REF 2N where N = 10 (bits), and D = the decimal value of the input code (0 to 1023).
Digital Interface
The MAX5841 features an I 2 C/SMBus-compatible 2-wire interface consisting of a serial data line (SDA) and a serial clock line (SCL). The MAX5841 is SMBus compatible within the range of VDD = 2.7V to 3.6V. SDA and SCL facilitate bidirectional communication between the MAX5841 and the master at rates up to 400kHz. Figure 1 shows the 2-wire interface timing diagram. The MAX5841 is a transmit/receive slave-only device, relying upon a master to generate a clock signal. The master (typically a microcontroller) initiates data transfer on the bus and generates SCL to permit that transfer. A master device communicates to the MAX5841 by transmitting the proper address followed by command and/or data words. Each transmit sequence is framed-
Output Buffer
The MAX5841 analog outputs are buffered by precision, unity-gain followers that slew 0.5V/s. Each buffer output swings rail-to-rail, and is capable of driving 5k in parallel with 200pF. The output settles to 0.5LSB within 4s.
Power-On Reset
The MAX5841 features an internal POR circuit that initializes the device upon power-up. The DAC registers
8
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Quad, 10-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC
Table 1. Power-Down Command Bits
POWER-DOWN COMMAND BITS PD1 0 0 PD0 0 1 Power-up device. DAC output restored to previous value. Power-down mode 0. Power down device with output floating. Power-down mode 1. Power down device with output terminated with 1k to GND. Power-down mode 2. Power down device with output terminated with 100k to GND. MODE/FUNCTION
STOP Conditions). Both SDA and SCL idle high when the I2C bus is not busy. START and STOP Conditions When the serial interface is inactive, SDA and SCL idle high. A master device initiates communication by issuing a START condition. A START condition is a high-tolow transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA, while SCL is high (Figure 2). A START condition from the master signals the beginning of a transmission to the MAX5841. The master terminates transmission by issuing a not acknowledge followed by a STOP condition (see Acknowledge Bit (ACK)). The STOP condition frees the bus. If a repeated START condition (Sr) is generated instead of a STOP condition, the bus remains active. When a STOP condition or incorrect address is detected, the MAX5841 internally disconnects SCL from the serial interface until the next START condition, minimizing digital noise and feedthrough. Early STOP Conditions The MAX5841 recognizes a STOP condition at any point during transmission except if a STOP condition occurs in the same high pulse as a START condition (Figure 3). This condition is not a legal I2C format; at least one clock pulse must separate any START and STOP conditions. Repeated START Conditions A REPEATED START (S r ) condition may indicate a change of data direction on the bus. Such a change occurs when a command word is required to initiate a read operation. S r may also be used when the bus master is writing to several I2C devices and does not want to relinquish control of the bus. The MAX5841 serial interface supports continuous write operations with or without an Sr condition separating them. Continuous
MAX5841
1
0
1
1
by a START (S) or REPEATED START (Sr) condition and a STOP (P) condition. Each word transmitted over the bus is 8 bits long and is always followed by an acknowledge clock pulse. The MAX5841 SDA and SCL drivers are open-drain outputs, requiring a pullup resistor to generate, a logic high voltage (see Typical Operating Circuit). Series resistors RS are optional. These series resistors protect the input stages of the MAX5841 from high-voltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals. Bit Transfer One data bit is transferred during each SCL clock cycle. The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high are control signals (see START and
SDA
tSU, DAT tLOW SCL tHIGH tHD, STA tR tF tHD, DAT
tSU, STA
tHD, STA
tBUF tSP tSU, STO
START CONDITION
REPEATED START CONDITION
STOP CONDITION
START CONDITION
Figure 1. 2-Wire Serial Interface Timing Diagram _______________________________________________________________________________________ 9
Quad, 10-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC MAX5841
S SCL Sr P
SDA
address. The serial interface compares each address value bit by bit, allowing the interface to power down immediately if an incorrect address is detected. The LSB of the address word is the Read/Write (R/W) bit. R/W indicates whether the master is writing to or reading from the MAX5841 (R/W = 0 selects the write condition, R/W = 1 selects the read condition). After receiving the proper address, the MAX5841 issues an ACK by pulling SDA low for one clock cycle. The MAX5841 has four different factory/user-programmed addresses (Table 2). Address bits A6 through A1 are preset, while A0 is controlled by ADD. Connecting ADD to GND sets A0 = 0. Connecting ADD to V DD sets A0 = 1. This feature allows up to four MAX5841s to share the same bus.
Figure 2. START and STOP Conditions
SCL SDA STOP START
Table 2. MAX5841 I2C Slave Addresses
LEGAL STOP CONDITION
PART MAX5841L
VADD GND VDD GND VDD
DEVICE ADDRESS (A6...A0) 0111 100 0111 101 1011 100 1011 101
SCL SDA
MAX5841L MAX5841M MAX5841M
START ILLEGAL STOP
ILLEGAL EARLY STOP CONDITION
Figure 3. Early STOP Conditions
read operations require Sr conditions because of the change in direction of data flow. Acknowledge Bit (ACK) The acknowledge bit (ACK) is the ninth bit attached to any 8-bit data word. ACK is always generated by the receiving device. The MAX5841 generates an ACK when receiving an address or data by pulling SDA low during the ninth clock period. When transmitting data, the MAX5841 waits for the receiving device to generate an ACK. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should reattempt communication at a later time. Slave Address A bus master initiates communication with a slave device by issuing a START condition followed by the 7-bit slave address (Figure 4). When idle, the MAX5841 waits for a START condition followed by its slave
10
Write Data Format In write mode (R/W = 0), data that follows the address byte controls the MAX5841 (Figure 5). Bits C3-C0 configure the MAX5841 (Table 3). Bits D9-D0 are DAC data. Bits S0 and S1 are sub-bits and are always zero. Input and DAC registers update on the falling edge of SCL during the acknowledge bit. Should the write cycle be prematurely aborted, data is not updated and the write cycle must be repeated. Figure 6 shows two example write data sequences. Extended Command Mode The MAX5841 features an extended command mode that is accessed by setting C3-C0 = 1 and D9-D6 = 0. The next data byte writes to the shutdown registers (Figure 7). Setting bits A, B, C, or D to 1 sets that DAC
S
A6
A5
A4
A3
A2
A1
A0
R/W
Figure 4. Slave Address Byte Definition
C3
C2
C1
C0
D9
D8
D7
D6
Figure 5. Command Byte Definition
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Quad, 10-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC MAX5841
MSB S A6 A5 A4 A3 A2 A1 A0 LSB R/W ACK MSB C3 C2 C1 C0 D9 D8 D7 LSB D6 ACK
MSB D5 D4 D3 D2 D1 D0 S1
LSB S0 ACK P
EXAMPLE WRITE DATA SEQUENCE MSB S A6 A5 A4 A3 A2 A1 A0 LSB R/W ACK MSB C3 C2 C1 C0 D9 D8 D7 LSB D6 ACK
MSB X X D C B A PD1
LSB PD0 ACK P
EXAMPLE WRITE TO POWER-DOWN REGISTER SEQUENCE
Figure 6. Example Write Command Sequences
to the selected power-down mode based on the states of PD0 and PD1 (Table 1). Any combination of the four DACs can be controlled with a single write sequence. Read Data Format In read mode (R/W = 1), the MAX5841 writes the contents of the DAC register to the bus. The direction of data flow reverses following the address acknowledge by the MAX5841. The device transmits the first byte of data, waits for the master to acknowledge, then transmits the second byte. Figure 8 shows an example read data sequence. I2C Compatibility The MAX5841 is compatible with existing I2C systems. SCL and SDA are high-impedance inputs; SDA has an open drain that pulls the data line low during the ninth clock pulse. The Typical Operating Circuit shows a typical I2C application. The communication protocol supports the standard I 2 C 8-bit communications. The general call address is ignored. The MAX5841 address is compatible with the 7-bit I2C addressing protocol only. No 10-bit address formats are supported.
X
X
D
C
B
A
PD1
PD0
Figure 7. Extended Command Byte Definition
Applications Information
Digital Inputs and Interface Logic
The MAX5841 2-wire digital interface is I 2C/SMBus compatible. The two digital inputs (SCL and SDA) load the digital input serially into the DAC. Schmitt-trigger buffered inputs allow slow-transition interfaces such as optocouplers to interface directly to the device. The digital inputs are compatible with CMOS logic levels.
Power-Supply Bypassing and Ground Management
Careful PC board layout is important for optimal system performance. Keep analog and digital signals separate to reduce noise injection and digital feedthrough. Use a ground plane to ensure that the ground return from GND to the power-supply ground is short and low impedance. Bypass V DD with a 0.1F capacitor to ground as close to the device as possible.
Digital Feedthrough Suppression
When the MAX5841 detects an address mismatch, the serial interface disconnects the SCL signal from the core circuitry. This minimizes digital feedthrough caused by the SCL signal on a static output. The serial interface reconnects the SCL signal once a valid START condition is detected.
Chip Information
TRANSISTOR COUNT: 17,213 PROCESS: BiCMOS
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11
Quad, 10-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC MAX5841
Table 3. Command Byte Definitions
C3 0 C2 0 C1 0 SERIAL DATA INPUT C0 D9 D8 0 DAC DATA DAC DATA D7 DAC DATA D6 DAC DATA FUNCTION Load DAC A input and DAC registers with new data. Contents of DAC B, C, and D input registers are transferred to the respective DAC registers. All outputs are updated. Load DAC B input and DAC registers with new data. Contents of DAC A, C, and D input registers are transferred to the respective DAC registers. All outputs are updated. Load DAC C input and DAC registers with new data. Contents of DAC A, B, and D input registers are transferred to the respective DAC registers. All outputs are updated. Load DAC D input and DAC registers with new data. Contents of DAC A, B, and C input registers are transferred to the respective DAC registers. All outputs are updated simultaneously. Load DAC A input register with new data. DAC outputs remain unchanged. Load DAC B input register with new data. DAC outputs remain unchanged. Load DAC C input register with new data. DAC outputs remain unchanged. Load DAC D input register with new data. DAC outputs remain unchanged. Data in all input registers is transferred to respective DAC registers. All DAC outputs are updated simultaneously. New data is loaded into DAC A input register. Data in all input registers is transferred to respective DAC registers. All DAC outputs are updated simultaneously. New data is loaded into DAC B input register. Data in all input registers is transferred to respective DAC registers. All DAC outputs are updated simultaneously. New data is loaded into DAC C input register. Data in all input registers is transferred to respective DAC registers. All DAC outputs are updated simultaneously. New data is loaded into DAC D input register. Load all DACs with new data and update all DAC outputs simultaneously. Input and DAC registers are updated with new data. Load all input registers with new data. DAC outputs remain unchanged.
0
0
0
1
DAC DATA
DAC DATA
DAC DATA
DAC DATA
0
0
1
0
DAC DATA
DAC DATA
DAC DATA
DAC DATA
0
0
1
1
DAC DATA DAC DATA DAC DATA DAC DATA DAC DATA DAC DATA
DAC DATA DAC DATA DAC DATA DAC DATA DAC DATA DAC DATA
DAC DATA DAC DATA DAC DATA DAC DATA DAC DATA DAC DATA
DAC DATA DAC DATA DAC DATA DAC DATA DAC DATA DAC DATA
0 0 0 0
1 1 1 1
0 0 1 1
0 1 0 1
1
0
0
0
1
0
0
1
DAC DATA
DAC DATA
DAC DATA
DAC DATA
1
0
1
0
DAC DATA
DAC DATA
DAC DATA
DAC DATA
1
0
1
1
DAC DATA
DAC DATA
DAC DATA
DAC DATA
1
1
0
0
DAC DATA DAC DATA
DAC DATA DAC DATA
DAC DATA DAC DATA
DAC DATA DAC DATA
1
1
0
1
12
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Quad, 10-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC MAX5841
Table 3. Command Byte Definitions (continued)
SERIAL DATA INPUT C3 1 1 1 1 1 1 C2 1 1 1 1 1 1 C1 1 1 1 1 1 1 C0 0 1 1 1 1 1 D9 X 0 0 0 0 1 D8 X 0 0 0 1 0 D7 X 0 0 1 0 0 D6 X 0 1 0 0 0 FUNCTION Update all DAC outputs simultaneously. Device ignores D9D6. Do not send the data byte. Extended command mode. The next word writes to the powerdown registers (Extended Command Mode). Read DAC A data. The device expects an Sr condition followed by an address word with R/W = 1. Read DAC B data. The device expects an Sr condition followed by an address word with R/W = 1. Read DAC C data. The device expects an Sr condition followed by an address word with R/W = 1. Read DAC D data. The device expects an Sr condition followed by an address word with R/W = 1.
MSB S A6 A5 A4 A3 A2 A1 A0
LSB R/W =0 ACK
MSB C3 C2 C1 C0 D9 D8 D7
LSB D6 ACK
DATA BYTES GENERATED BY MASTER DEVICE MSB Sr A6 A5 A4 A3 A2 A1 A0 LSB R/W =1 ACK MSB X X PD1 PD0 D9 D8 D7 LSB D6 ACK
DATA BYTES GENERATED BY MAX5841
ACK GENERATED BY MASTER DEVICE
MSB D5 D4 D3 D2 D1 D0 S1
LSB S0 ACK P
Figure 8. Example Read Word Data Sequence
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13
Quad, 10-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC MAX5841
Functional Diagram
REF
INPUT REGISTER A
MUX AND DAC REGISTER
10-BIT DAC A
MAX5841 OUTA RESISTOR NETWORK
INPUT REGISTER B
MUX AND DAC REGISTER
10-BIT DAC B RESISTOR NETWORK
OUTB
INPUT REGISTER C
MUX AND DAC REGISTER
10-BIT DAC C RESISTOR NETWORK
OUTC
INPUT REGISTER D
MUX AND DAC REGISTER
10-BIT DAC D RESISTOR NETWORK
OUTD
SERIAL INTERFACE
POWER-DOWN CIRCUITRY
SDA ADD SCL
VDD
GND
14
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Quad, 10-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC
Package Information
10LUMAX.EPS
MAX5841
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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